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REVISION AND PRACTICE

Week 4 Quick Revision

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Start here All of Week 4 on one page: what each block does, its key formula, the facts that keep coming back as true/false questions, and 10 practice questions.

Four blocks: comparator, decoder, encoder (and priority encoder), and multiplexer.
Four blocks: comparator, decoder, encoder (and priority encoder), and multiplexer.
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Week 4 at a glance

The whole week in a table

Block Inputs → outputs Key formula / fact
Equality comparator two n-bit numbers → 1 bit XNOR per bit, then AND all
Decoder n→2nn \to 2^{n} Exactly one output is 1. Each output is a minterm
Encoder 2n→n2^{n} \to n 4-to-2:Y1=I2+I3,Y0=I1+I32 : Y_{1} = I_{2} + I_{3} , Y_{0} = I_{1} + I_{3}
Priority encoder 2n→n2^{n} \to n Highest active input wins. Y1=I3+I2,Y0=I3+I2‾I1Y_{1} = I_{3} + I_{2} , Y_{0} = I_{3} + \overline{I_{2}} I_{1}
Multiplexer N data + log₂N select → 1 2:1:Y=S‾I0+SI12 : 1 : Y = \overline{S} I_{0} + S I_{1}

Numbers to remember

  • 2:1 MUX delay = NOT⁡+AND⁡+OR⁡\operatorname{NOT} + \operatorname{AND} + \operatorname{OR} (all 1 ns → 3; NOT 1, AND/OR 2 → 5).
  • Decoder delay = NOT⁡+AND⁡\operatorname{NOT} + \operatorname{AND} (a 3-input AND made of 2-input ANDs counts twice).
  • 2:1 MUX counts: AND 1, OR 1, NOT 1, XOR 2, XNOR 2, NAND 2, NOR 2.
  • Select lines for an N:1MUX⁡=N : 1 \operatorname{MUX} = log₂N.

Common mistakes

Mistake Correct way
Adding delays of gates that work side by side Only add gates in a chain
Treating NOT as free in MUX-count questions NOT⁡=\operatorname{NOT} = 1 MUX (unless the question gives X‾\overline{X})
Plain encoder with two inputs on Gives a wrong code; that’s why we need priority encoders
Missing a bent wire in a decoder circuit Trace every wire to see which Dₖ goes into the OR
Trusting an option that “looks right” Put in numbers and test (one past key was wrong!)

Practice questions

  1. How many outputs does a 4-input decoder have?
16.
  1. A 3:8 decoder gets ABC=011A B C = 0 1 1. Which output is 1?
D3D_{3}.
  1. F(A,B,C)=Σm(0,7)F \left(A , B , C\right) = \Sigma m \left(0 , 7\right) using a 3:8 decoder. What extra gate?
One 2-input OR gate on D0D_{0} and D7D_{7}.
  1. 4-to-2 priority encoder, inputs I3I2I1I0=0110I_{3} I_{2} I_{1} I_{0} = 0 1 1 0. Output?
101 0 (I₂ is the highest input that is on).
  1. How many select lines does a 16:1 MUX have?
4.
  1. 2:1MUX⁡,NOT⁡=22 : 1 \operatorname{MUX} , \operatorname{NOT} = 2 ns, AND⁡=OR⁡=1\operatorname{AND} = \operatorname{OR} = 1 ns. Maximum delay?
2 + 1 + 1 = 4 ns.
  1. Minimum 2:1 MUXes for A⊕BA \oplus B?
2 (one makes B‾\overline{B}, one picks B or B‾\overline{B} using A).
  1. 2:1 MUX with S=A,I0=0,I1=BS = A , I_{0} = 0 , I_{1} = B. What gate is it?
AND⁡(Y=AB)\operatorname{AND} \left(Y = A B\right).
  1. 4-bit equality comparator: A=1100,B=1101A = 1 1 0 0 , B = 1 1 0 1. Output?
0 (bit 0 differs).
  1. True or false: “In a decoder, exactly one of the outputs is 1 at any time.”
True.
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