REVISION AND PRACTICE

Week 3 Quick Revision

3 min read
On this page 3 headings

Start here Ten minutes before the exam? Read this page. It has every Week 3 idea in one place, plus practice questions in the exam’s style.

Truth table → SOP or POS → two-level circuit → NAND/NOR only → count the gates.
Truth table → SOP or POS → two-level circuit → NAND/NOR only → count the gates.
Open image ↗
Week 3 at a glance

The whole week in 8 lines

  1. SOP → circuit: NOTs → one AND per term → one OR. This is two-level logic.
  2. Canonical ≠ minimal. Σm(3,4,5,6,7)=\Sigma m \left(3 , 4 , 5 , 6 , 7\right) = A+BCA + B C.
  3. POS uses the 0-rows. Each gives a maxterm: 0→A,1→A‾0 \to A , 1 \to \overline{A}, joined by OR. Then AND them all.
  4. Σ ↔︎ Π → use the missing numbers. F ↔︎ F‾\overline{F} → also the missing numbers. Both → the same numbers.
  5. NAND and NOR are universal. Each one alone can build anything.
  6. Gate counts: NAND: NOT 1, AND 2, OR 3, XOR 4, XNOR 5. NOR: NOT 1, OR 2, AND 3, XNOR 4, XOR 5.
  7. AND–OR⁡=NAND⁡\operatorname{OR} = \operatorname{NAND}–NAND, and OR–AND⁡=NOR⁡\operatorname{AND} = \operatorname{NOR}–NOR (same shape, swap the gates).
  8. Timing diagram: slice wherever an input changes → truth table → simplify. “Any one flip changes the output” = XOR.

Common mistakes

Mistake Correct way
Using the SOP literal rule for maxterms Maxterm: 0→A,1→A‾0 \to A , 1 \to \overline{A}
Treating a NOT as free in a NAND-only circuit Every NOT costs 1 NAND
Counting gates before simplifying Simplify first. The answer may be just 1
Counting terms instead of literals “ab+a‾c‾a b + \overline{a} \overline{c}” has 4 literals
Forgetting rows go to 15 for 4 variables Rows = 0 to 2ⁿ − 1

Practice questions

  1. F(A,B,C)=Σm(0,1,5)F \left(A , B , C\right) = \Sigma m \left(0 , 1 , 5\right). Write F as ΠM\Pi M.
ΠM(2,3,4,6,7)\Pi M \left(2 , 3 , 4 , 6 , 7\right).
  1. Write the maxterm for row A=0,B=1,C=1A = 0 , B = 1 , C = 1.
(A+B‾+C‾),M3\left(A + \overline{B} + \overline{C}\right) , M_{3}.
  1. Minimum 2-input NAND gates for an OR gate?
3.
  1. Minimum 2-input NOR gates for a 1-bit equality checker (1 when A=BA = B)?
4 (it’s XNOR).
  1. F=(X‾+Y‾)(Z+W)F = \left(\overline{X} + \overline{Y}\right) \left(Z + W\right). Minimum 2-input NAND gates?
  1. G1 = NAND(X,Y) gives X‾+Y‾\overline{X} + \overline{Y} for free; G2 = NAND(Z,G1); G3 = NAND(W,G1); F=NAND⁡F = \operatorname{NAND}(G2,G3).
  1. Minimum literals in ab+a‾b‾c‾+a‾bc‾a b + \overline{a} \overline{b} \overline{c} + \overline{a} b \overline{c}?
4 (it simplifies to ab+a‾c‾a b + \overline{a} \overline{c}).
  1. A timing diagram shows Y=1Y = 1 whenever an odd number of A, B, C are 1. Minimum 2-input XOR gates?
2(Y=A⊕B⊕C)2 \left(Y = A \oplus B \oplus C\right).
  1. True or false: an AND–OR circuit becomes a NOR–NOR circuit when you swap every gate for NOR.
False. AND–OR becomes NAND–NAND. It’s OR–AND that becomes NOR–NOR.
  1. Why might a designer choose a multilevel circuit over a two-level one?
It usually needs fewer gates (cheaper and smaller), even though it is a bit slower.
  1. F=ΠM(2,5)F = \Pi M \left(2 , 5\right). Write F‾\overline{F} as Σm\Sigma m.
Σm(2,5)\Sigma m \left(2 , 5\right).
YOUR STUDY PROGRESS

Finished this section? Save your progress.

Back to top ↑