REVISION AND PRACTICE
Week 3 Quick Revision
On this page 3 headings
Start here Ten minutes before the exam? Read this page. It has every Week 3 idea in one place, plus practice questions in the exam’s style.
- SOP → circuit: NOTs → one AND per term → one OR. This is two-level logic.
- Canonical ≠ minimal. .
- POS uses the 0-rows. Each gives a maxterm: , joined by OR. Then AND them all.
- Σ ↔︎ Π → use the missing numbers. F ↔︎ → also the missing numbers. Both → the same numbers.
- NAND and NOR are universal. Each one alone can build anything.
- Gate counts: NAND: NOT 1, AND 2, OR 3, XOR 4, XNOR 5. NOR: NOT 1, OR 2, AND 3, XNOR 4, XOR 5.
- AND––NAND, and OR––NOR (same shape, swap the gates).
- Timing diagram: slice wherever an input changes → truth table → simplify. “Any one flip changes the output” = XOR.
| Mistake | Correct way |
|---|---|
| Using the SOP literal rule for maxterms | Maxterm: |
| Treating a NOT as free in a NAND-only circuit | Every NOT costs 1 NAND |
| Counting gates before simplifying | Simplify first. The answer may be just 1 |
| Counting terms instead of literals | “” has 4 literals |
| Forgetting rows go to 15 for 4 variables | Rows = 0 to 2ⁿ − 1 |
- . Write F as .
.
- Write the maxterm for row .
.
- Minimum 2-input NAND gates for an OR gate?
3.
- Minimum 2-input NOR gates for a 1-bit equality checker (1 when )?
4 (it’s XNOR).
- . Minimum 2-input NAND gates?
- G1 = NAND(X,Y) gives for free; G2 = NAND(Z,G1); G3 = NAND(W,G1); (G2,G3).
